We present an overview for proposed general architecture of the CLEO III front-end electronics, trigger, and data acquisition systems. This has been driven by several conditions:
The primary goal of the detector upgrade is to operate with
CESR Phase 3 at luminosities up to
cm
s
and to easily
accommodate
. The exact accelerator bunch structure that
will achieve these luminosities is uncertain at this time, ranging from nine
bunch trains with 5 sub-bunches to almost
continuous bunches 14 ns apart. Clearly, any CLEO III design choices must
be compatible with any machine bunch structure.
Particle and synchrotron radiation background rates are uncertain. Different CESR topologies make their prediction even more uncertain. Furthermore, extrapolations to luminosities fifty times greater than today cannot be viewed as reliable. From discussions below, we will see that background rates in detectors near the beam pipe can be as high as 100 kHz.
Some CLEO III electronics cannot easily be upgraded to
to accommodate the full reach of CESR luminosity beyond Phase 3.
Among these systems are the
front-end electronics (preamps, data boards, and the trigger information
derived from the front-end boards), the board and crate level event
buffering, the crate back-plane technology, and the fast timing
system including event flow control. The electronics architecture
must accommodate operation beyond just as the
CLEO I and II architecture will have accommodated 15 years of luminosity
improvements.
Items that are required to operate CLEO and that can be enhanced or upgraded include the hardware trigger processors and decision logic, the event builder data collection and assembling, the level 2 trigger, the level 3 trigger implementation, and the data delivery mechanism to the event builder/level 3 trigger processor(s).
We briefly state the modifications required for the CLEO III detector.
In the trigger system we eliminate the lowest level trigger which
is driven by the beam crossing rate; track and energy information can
be used in coincidence in the lowest level trigger; the deadtime is
determined by the level 2 trigger latency, 10
s.
In the drift chamber we preserve sub-nanosecond timing precision
with memory times up to 2.5
s; both charge and time measurements
are performed; and multi-hit capability is provided to deal
with track congestion and pile-up at small radii. The silicon detector
requires an on-detector front-end IC optimized for use in CLEO which
digitizes and buffers data in 10
s and may provide trigger
information. The particle ID system requires development of a preamp
and readout electronics. The CsI and muon systems have their
readout electronics upgraded for 10
s conversion and data buffering.
A new DAQ architecture is used to readout the detector at up to 1 kHz
with little or no dead-time impact by using several levels of buffering
to allow overlapped readout and acquisition.