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Gating and event flow control

The gating logic interfaces to the CESR timing systems using components from the accelerator master timing system. The various gates and clocks used by the front-end and trigger systems and their synchronization with the beam bunch crossings are implemented with these CESR components. The timing system will be packaged in VME and be remotely software programmable.

The event flow control system and its network coordinate the DAQ, trigger, and gating systems. Gates, level 1 and level 2 trigger accepts, level 2 trigger aborts, and event numbers are distributed to the crates. Control of programmable calibration pulsers is also done here. Data collected via this network are the event buffer availability in front-end boards, front-end crates, and event builder memories. A grand OR of the status of these systems is used to inhibit-throttle-further event triggers to the front-ends.

It may be impossible to measure the individual luminosity of each bunch crossing in CESR. This is the motivation for having the level 1 trigger in continuous operation even when the DAQ system cannot handle more events. The throttle signals from DAQ convert successful level 1 triggers into failures. The gating and event flow control system provides scalers to record this activity allowing a reliable dead-time correction to be made to the off-line calculated luminosity.

An additional feature required of the event flow control network is a mechanism to perform a back-plane reset in the VME and FASTBUS crates. This is usual to recover from processor ``hangs'' that require system resets.


bebek@lns598.lns.cornell.edu