New front-end electronics will be required for several reasons.
First and
foremost, we must significantly reduce the readout dead-time. Although
the present hardware supports a rather cumbersome way of halving this
time, the improvement of a factor of twenty that
we seek can not be realized without a complete redesign of the front-end
digitizing and buffering hardware. Secondly, waiting 2.5
s
after a good event's crossing for the trigger to assert
dead-time means that single-hit electronics will effectively integrate
over this time. This may not be acceptable in view of synchrotron-radiation
background levels, especially in the inner regions of the tracking volume.
The solution is to implement multi-hit front-end electronics, particularly in
the regions of high occupancy, but preferably throughout the entire tracking
system in order to maintain uniformity of architecture.
The design goal of the front-ends will be to digitize and buffer the
entire detector in less than 100 s, preferably less than 10
s.
This will give a readout induced dead-time of 1-10%at a 1000 Hz
event-rate limit. This is acceptable for any foreseeable luminosity
upgrade. Dead-time from a system having the trigger and front-end
characteristics discussed in the above sections is shown in
Table
. Block diagrams of the
front-end system components are shown in Fig. .
Drift chamber
A preamp will be mounted at the drift chamber endplates. This will
provide some shaping and line driving ability. The signal is not
discriminated here because we are interested in the wire charge for
d/d
measurements. To help reduce the mass at the endplates,
monolithic preamps will be investigated. Smaller connectors and thinner
cables to the crates boards will help to free up valuable space.
There are possible commercial solutions available for implementing a multi-hit
front-end system. LeCroy has introduced an interesting timing circuit, the
MTD133, that records the value of a 16-bit counter for up to 16 input
transitions. A common stop signal records a final clock value and prepares the
circuit for readout at which time the final clock value is subtracted from
each of the up to 16 time recordings. The time resolution is 0.75 ns and the maximum depth
is 40 s.
Set up to record times on both rising and falling edges, the MTD133 can also be
used as the counter in a Wilkinson run-down ADC. An experiment at CEBAF will
multiplex timing and charge information into the same MTD133 channel using
pulse width as markers. In future versions of the MTD133, LeCroy promises
several additional features, including 0.5 ns resolution over a 32 s
range. Since Lecroy has not yet produced an MTD133 with the required
performance, we must carefully evaluate other commercial solutions and the
system used in other experiments.
The use of commercial TDC/ADC's will require a separate development of a system to split the preamp signals into timing and charge chains. The timing chain requires a discriminator whose output is compatible with the TDC. The charge chain may need to integrate the signal depending on the charge measuring scheme-TDC or ADC. The timing chain may need to provide the wire hit information to the trigger system. For some LeCroy FASTBUS modules this is available on the auxiliary connector.
Calorimeter
The present ADC system provides 12-bit resolution on two scales to give 15-bit
dynamic range. It requires 750 s to convert. It is not self-sparsifying,
does not have multi-event storage, nor does it allow simultaneous read and
write. Desirable features of any new ADC system are increased resolution, 14
bits with a 17-bit dynamic range, and lower coherent noise. The present ADC
resolution is comparable to the noise and it would be nice to better resolve
the pedestal to study coherent versus incoherent noise contributions. The
preamps and mixer-shaper system will be retained with some re-work of the
trigger section. To use the analog trigger sums at the mixer-shaper card level
requires a new upper back-plane.
Multi-hit electronics for the calorimeter is not a requirement.
The design of the level 1 trigger has been constrained to make a
decision before 2.5 s specifically for the purpose of gating the
calorimeter conversion hardware, and we will use this to greatly simplify
these front-ends. A single-hit system with sufficient dynamic range can
be constructed by viewing each crystal with a pair of 14-bit ADC's in
a dual-range configuration. The ADC outputs are stored in moderate
depth FIFO's that are read out over a digital back-plane asynchronous to
the trigger. The requirement that this system convert
and buffer its data at the 10
s time scale (for a reasonable cost)
is not particularly
onerous given recent developments in commercial ADC technology.
While two ADC's per channel may appear excessive, it avoids the
expense and bulk of fast, precision analog multiplexors. In addition,
massively parallel digitizing and buffering at the front-end opens up
the possibility of doing intelligent sparsification in the front-end
crates, removing any bandwidth bottleneck presently associated with
the ``slightly parallel'' DAQ90 sparsification scheme.
The use of the MTD133 for precision calorimetry is unclear at this time.
With a dual range system where each charge is measured to 12-bit precision,
a given crystal signal can occupy up to 4096 of the 65535 counts
of the MTD133 time
span. This essentially introduces an additional 3 s crystal dead-time
for each hit that starts the integrate/ramp-down process.
This is probably not a problem since the occupancy of the crystals is small.
There are other fast converting ADC systems commercially available.
Muons A single range version of the gated integrator ADC's used for the CsI will work in the muon system. A preamplifier-shaper specific to the muon system will need to be developed.
Silicon
On-detector silicon readout electronics is always multiplexed due to space,
density, and power dissipation limits. It can easily define the performance
of the DAQ system. We require an analog-storage silicon front-end (for best
spatial resolution) that converts and buffers its data in 10-50 s and
allows overlapped readout and acquisition. On-chip sparsification can help to
meet this goal. Serial-bus interfaces to the IC's can reduce the bulk of the
cable plant.
It is probably beyond the means of the CLEO collaboration to develop an
entirely new silicon readout integrated circuit. Happily, this is an area of
much activity in the HEP community. D0 and CDF are building new detectors
based on the SVX-II circuit that provides analog pipelining, on-board
digitization, and sub-10 s readout. Two LHC R&Dprojects, RD2 and RD20,
are developing analog pipelined, simultaneous write/read silicon front-ends.
The time scale of these developments and others may be compatible with CESR
phase 3 and it behooves us to leverage off these efforts. Modification of
another experiment's electronics to CLEO specifications is definitely within
the abilities of the collaboration. One area of customization is to provide
strip OR's for triggering purposes. The selection of an existing front-end IC
will depend on its compatability with the detector strip pitch, noise
performance, and tolerance to an integrated radiation dose of
1 Mrad.
The crate-based data boards that will control and receive data from the detectors will probably be specific to CLEO. These entail sequencers, FIFO's, sparsification logic, and multi-event buffers.
Particle ID
Since a particle ID scheme has not been chosen, the design of the relevant
front-ends is not possible at this time. We will simply decree that the
parameters of such a system will have to fit within the constraints described
above, namely that it must be able to tolerate a 2.5 s delay between
the actual event and the time it is ``strobed'' and that converting
and buffering the data should take
10
s.
Trigger systems The trigger system has another role as a source of event data. Like the other front-end systems, it must buffer multiple events at the individual board level and at the crate level.